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SoCs测试访问机制的算法设计

发表时间:2015-08-31  浏览量:1452  下载量:453
全部作者: 靖固,白银平
作者单位: 哈尔滨理工大学计算机科学与技术学院
摘 要: 以ITC’02 测试基准电路SoC d695 为基础,建立SoCs 系统芯片的层次化测试结构模型。运用软/硬件协同设计的思想对测试结构模型进行设计与优化,设计相应的多级测试访问机制,提出了SoCs 组式带宽灵活分配测试访问机制(test access mechanism,TAM)测试策略。在测试调度控制时,采用宏模块控制的思想加以实现。将SoCs 层次化测试结构分而治之,并行测试,增加测试的灵活性,从而提高测试效率,节约测试时间,对于目前日益复杂化的层次型SoCs 的可测试实现与优化研究具有重大的现实意义。
关 键 词: 计算机处理器技术;SoCs测试结构;多级测试访问机制;测试策略;Wrapper设计
Title: Implementation of test access mechanism for SoCs
Author: JING Gu, BAI Yinping
Organization: School of Computer Science and Technology, Harbin University of Science and Technology
Abstract: Based on the SoC d695 in ITC’02 benchmark circuits, the hierarchical structure model of SoCs testing system chips was established. Using hardware and software co-design idea to design and optimize the test structure model, we designed the corresponding multi-level test access mechanism and proposed a testing strategy of grouped SoCs flexible bandwidth test access mechanism (TAM). In the test of scheduling control, macro-control module was adopted. In order to increase the flexibility of the test, improve test efficiency and save testing time, the hierarchical test structure of SoCs was used as parallel test, which had great practical significance for testable realization of increasing complex hierarchical SoCs and optimization study.
Key words: computer processor technology; SoCs test structure; parallel test access mechanism; test stragy; Wrapper design
发表期数: 2015年8月第16期
引用格式: 靖固,白银平. SoCs测试访问机制的算法设计[J]. 中国科技论文在线精品论文,2015,8(16):1702-1708.
 
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