您的位置:首页  > 论文页面

一种用于无人机的改进RC-LDPC码及实现

发表时间:2017-08-31  浏览量:191  下载量:25
全部作者: 赵旦峰,王艺霖
作者单位: 哈尔滨工程大学信息与通信工程学院
摘 要: 针对无人机应用环境复杂化、通信要求多样化的问题,提出一种基于渐进边增长(progress edge growth,PEG)算法的码率兼容低密度奇偶校验(rate-compatible low-density parity-check,RC-LDPC)码的改进构造法,并通过此构造法设计可涵盖多个码率的校验码。仿真结果表明,该矩阵在实现码率兼容的同时,其性能优于参数相近条件下的单一码率的传统QC-LDPC. 针对该码型,设计一种通过调用随机存储器RAM的编码器,该架构可以减少无人机上的资源使用,同时有效实现多码率多码长的切换。最后,采用Verilog HDL硬件描述语言在Cyclone IV系列FPGA芯片上实现了编码器。综合结果表明,该编码架构在有效减少循环移位存储器使用的同时有效降低了资源占比,可以满足无人机的资源使用要求。
关 键 词: 信息处理技术;码率兼容低密度奇偶校验;渐进边增长;现场可编程门阵列(FPGA)
Title: An improved RC-LDPC code for UAV and its implementation
Author: ZHAO Danfeng, WANG Yilin
Organization: College of Information and Communication Engineering, Harbin Engineering University
Abstract: In order to solve the problem of complexity in the application environment and the requirements of communication on UAV, an improved construction of rate-compatible low-density parity-check (RC-LDPC) codes based on progress edge growth (PEG) is proposed, and a code which can cover several rates is designed. The simulation result shows that this code covers multi-rates, and the performance of this code is better than other traditional QC-LDPC codes with single rate. An encoder based on RAM is designed for the type of this code. The structure of encoder can reduce the use of source in the UAV and its implementation of the encoder is accessible to cover multi-rates and multi-flames. The encoder is implemented on the FPGA chip of Cyclone IV with Verilog HDL language. The results show that the encoder reduces the application of the cyclic shift memory and the occupancy of the chip resource at the same time, and it could reach the requirement of an UAV resource.
Key words: information processing technology; rate-compatible low-density parity-check; progress edge growth; field programmable gate array (FPGA)
发表期数: 2017年8月第16期
引用格式: 赵旦峰,王艺霖. 一种用于无人机的改进RC-LDPC码及实现[J]. 中国科技论文在线精品论文,2017,10(16):1799-1804.
 
1 评论数 0
暂无评论
友情链接