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一种MIPI协议高速接口D-PHY物理层电路设计

发表时间:2021-06-19  浏览量:219  下载量:54
全部作者: 张震,娄珊珊,刘岩,杨刚,王冠然,常玉春
作者单位: 大连理工大学微电子学院
摘 要: 采用SMIC 0.18 µm 互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)工艺设计了一种适用于高速接口的速度更快、性能更优的MIPI D-PHY物理层电路,包括带占空比校正的时钟通道模块、高速发射器(high-speed transmitter,HS-TX)模块、高速接收器模块(high-speed receiver,HS-RX)、低功耗发射器模块(low-power transmitter,LP-TX)、低功耗接收器(low-power receiver,LP-RX)模块和低功耗冲突检测器(low-power conflict detector,LP-CD)模块。各模块的仿真结果均满足MIPI协议规范要求。在高速模式下时钟占空比校正的精度为±0.5%,单通道信号传输速率达到2 Gbls,低功耗模式下的信号传输速率不大于10 Mbls,功耗为2.8 mW,抖动仅为8 ps,远小于标准要求的32 ps.
关 键 词: 电子技术;MIPI D-PHY;物理层;占空比校正;高速;低抖动
Title: Design of a MIPI protocol high-speed interface D-PHY physical layer circuit
Author: ZHANG Zhen, LOU Shanshan, LIU Yan, YANG Gang, WANG Guanran, CHANG Yuchun
Organization: School of Microelectronics, Dalian University of Technology
Abstract: In this paper, the SMIC 0.18 µm complementary metal oxide semiconductor (CMOS) technology is used to design a faster and better performance MIPI D-PHY physical layer circuit for high-speed interfaces. It includes clock channel module with duty-cycle correction, high-speed transmitter (HS-TX) module, high-speed receiver (HS-RX) module, low-power transmitter (LP-TX) module, low-power receiver (LP-RX) module and low-power conflict detector (LP-CD) module. The simulation results of each module meet the requirements of the MIPI protocol specification. In high-speed mode, the accuracy of clock duty-cycle correction is ±0.5%, the single-channel signal transmission rate reaches 2 Gbls. In low-power mode, the signal transmission rate is not more than 10 Mbls, the power consumption is 2.8 mW, and the jitter is only 8 ps, far less than 32 ps required by the standard.
Key words: electronic technology; MIPI D-PHY; physical layer; duty-cycle correction; high speed; low jitter
发表期数: 2021年6月第2期
引用格式: 张震,娄珊珊,刘岩,等. 一种MIPI协议高速接口D-PHY物理层电路设计[J]. 中国科技论文在线精品论文,2021,14(2):237-245.
 
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