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基于总线复用技术的低成本NAND测试方法

发表时间:2021-06-19  浏览量:145  下载量:32
全部作者: 杜发魁,郭筝
作者单位: 晟碟信息科技(上海)有限公司;上海交通大学电子信息与电气工程学院
摘 要: 随着NAND闪存芯片的存储容量持续增加,测试时间所带来的成本增加问题越发严重,本文围绕着如何降低单位测试时间和测试成本这一核心问题展开。在对闪存测试项目、测试方法分析的基础上,结合自动化测试设备(automatic test equipment,ATE)并行同测方法,提出新的输入输出总线复用测试方法,从而缓解闪存测试时间长、测试成本高的问题。以特定测试机台T5773为例,重新设计软硬件将测试机的并行测试吞吐率增加一倍,并对本设计中的一些基本问题如失效处理等进行了说明和解决办法汇总,最终减少单位测试时间44.4%,极大降低了闪存测试成本。因此,此方法可以运用于闪存大规模生产的成本控制。
关 键 词: 半导体技术;集成电路测试;NAND闪存;减少测试时间;总线复用
Title: Low cost NAND testing method based on bus reuse
Author: DU Fakui, GUO Zheng
Organization: SanDisk Information Technology (Shanghai) Co., Ltd.; School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University
Abstract: As the storage capacity of NAND flash memory chips continues to increase, the cost increase caused by test time becomes more and more serious. We focus on the core issue of how to reduce the unit test time and test costs in this paper. Based on the analysis of the flash memory test items and test methods, combined with the automatic test equipment (ATE) parallel test method, a new input and output bus reuse test method is proposed to alleviate the long test time and high test cost of the flash memory. Taking the specific test machine T5773 as an example, the software and hardware were redesigned to double the parallel test throughput rate of the test machine, and some basic problems in the design, such as failure handling, were explained and the solutions were summarized, which ultimately reduced the unit test time at 44.4% and then greatly reduced the cost of flash memory test. Therefore, this method can be used for cost control in mass production of flash memory.
Key words: semiconductor technology; integrated circuit testing; NAND flash memory; test time reduction; bus reuse
发表期数: 2021年6月第2期
引用格式: 杜发魁,郭筝. 基于总线复用技术的低成本NAND测试方法[J]. 中国科技论文在线精品论文,2021,14(2):246-252.
 
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