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基于FPGA的EtherCAT主站设计研究
发表时间：2017-01-23 浏览量：3083 下载量：775
| 全部作者： | 董伯麟，张越盈 |
| 作者单位： | 合肥工业大学机械工程学院 |
| 摘 要： | 提出一种基于现场可编辑逻辑门阵列（field-programmable gate array，FPGA）的以太网控制自动化技术（Ethernet for control automation technology，EtherCAT）的主站实现方案。以软核方式用Nios II实现协议栈，包括应用层、数据链路层及网卡驱动；主站时钟以FPGA实现普通晶振的频率补偿，使主站以稳定时钟频率同步于参考时钟；实现主站与伺服驱动器之间的通信与运动控制。实验表明，基于FPGA软核的EtherCAT主站不仅可以纳秒级同步时间控制整个主从系统，实现与伺服通信和控制的任务，还可充分利用FPGA的逻辑单元，节省硬件资源，并且所有模块均可在FPGA上实现，为高速、高精度、多通道数控（computer numerical control，CNC）技术的实现提供一种紧凑快捷的解决方案。 |
| 关 键 词： | 数控技术；现场可编辑逻辑门阵列；以太网控制自动化技术协议；现场总线；开放系统互连参考模型 |
| Title： | EtherCAT master station study based on FPGA |
| Author： | DONG Bolin, ZHANG Yueying |
| Organization： | School of Mechanical Engineering, Hefei University of Technology |
| Abstract： | This paper puts forward a kind of Ethernet for control automation technology (EtherCAT) master implementation scheme based on field-programmable gate array (FPGA) with soft core Nios II to achieve protocol stack, including application layer, data link layer and the network card drive. The master clock in FPGA achieves common crystal oscillator frequency compensation and enables the primary station to stabilize clock frequency synchronization to the reference clock. Communication and motion control between the master station and the servo drive are achieved. Experimental results show that based on FPGA soft core, EtherCAT master station not only can control the master-slave system with nanosecond synchronization time and realize the task with the communication and control of servo, but also can make full use of the FPGA logic unit, saving hardware resources and all the modules can be implemented in FPGA, offering a compact and efficient solution for realizing the computer numerical control (CNC) technology of high speed, high precision and multi channels. |
| Key words： | numerical control technology; field-programmable gate array; Ethernet for control automation technology protocol; field bus; open system interconnection reference model |
| 发表期数： | 2017年1月第2期 |
| 引用格式： | 董伯麟，张越盈. 基于FPGA的EtherCAT主站设计研究[J]. 中国科技论文在线精品论文，2017，10（2）：131-136. |
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