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高线性、高注入效率CTIA单元电路的设计

发表时间:2009-09-30  浏览量:1559  下载量:737
全部作者: 文勇,夏晓娟,孙伟峰
作者单位: 东南大学国家专用集成电路系统工程技术研究中心
摘 要: 分析了传统的电容跨阻抗放大器(capacitive transimpedance amplifier, CTIA)读出电路单元电路放大器的优缺点,提出了一种改进型的CTIA单元结构,它由共源共栅电流镜做负载的单级放大器组成,采样电路采用相关双采样技术(correlated double sampling,CDS)。该改进型电路能很好地控制探测器偏压,提高CTIA单元电路的线性度和注入效率;采用倒宽长比设计该放大器,可以降低功耗;采用CDS结构降低采样开关的热噪声。具体电路采用0.5 μm DPTM CMOS工艺设计,仿真结果表明:改进型CTIA单元电路的探测器偏压稳定性好,输出的线性度和注入效率高。另外,该单元电路结构简单,性能受工艺偏差影响小,适用于大阵列红外焦平面读出电路。
关 键 词: 微电子学;电容跨阻抗放大器;探测器偏压;注入效率;线性度;相关双采样技术
Title: The design of CTIA readout integrated circuit with high linearity and high injection efficiency
Author: WEN Yong, XIA Xiaojuan, SUN Weifeng
Organization: National Application Specific Integrated Circuit System Engineering Research Center, Southeast University
Abstract: This paper analyzed advantages and disadvantages of traditional capacitive transimpedance amplifier (CTIA) unit circuit amplifier and proposed an improved CTIA unit circuit with a load of cascode current mirror. The sample circuit introduces the correlated double sampling (CDS) technique. The improved circuit can make the detector bias more stable and increase the linearity and injection efficiency. The amplifier has been designed with reversed W/L in order to obtain low power. The CDS technique can reduce the kT/C noise engendered by sample switch. Simulation results based on 0.5 μm DPTM CMOS technology show that the stability of the detector bias of the improved circuit is the best. Its injection efficiency and linearity are increased. In addition, due to the simple structure of the improved circuit and its perfect performance of technology deviations, it is very suitable for the great infrared focal plane arrays.
Key words: microelectronics; capacitive transimpedance amplifier; detector bias; injection efficiency; linearity; correlated double sampling
发表期数: 2009年9月第18期
引用格式: 文勇,夏晓娟,孙伟峰. 高线性、高注入效率CTIA单元电路的设计[J]. 中国科技论文在线精品论文,2009,2(18):1869-1874.
 
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