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MP3音频解码器的硬件设计与FPGA实现

发表时间:2009-09-30  浏览量:2034  下载量:1037
全部作者: 张多利,杜伏慧,杜高明,宋宇鲲
作者单位: 合肥工业大学微电子设计研究所
摘 要: 在研究MP3解码算法的基础上,采用基于硬件的实现方法完成了MP3解码器的设计。根据硬件实现的特点对算法进行了优化,使用Verilog HDL语言实现了MP3解码器的寄存器传输级(register transfer level, RTL)设计,并完成了功能仿真验证。然后,基于ALTERA的StratixII EP2S180器件,完成了现场可编程门阵列(field-programmable gate array, FPGA)硬件原型设计,并在FPGA原型上实现了实时解码的声音播放演示。主观评测效果良好,解码信噪比(signal-to-noise ratio, SNR)达到89 dB,优于MP3解码的一般要求。
关 键 词: 微电子与固体电子学;MP3解码器;硬件实现;现场可编程门阵列原型
Title: A case study on hardware architecture and FPGA prototype implementation of MP3 audio decoder
Author: ZHANG Duoli, DU Fuhui, DU Gaoming, SONG Yukun
Organization: Institute of Micro-electronics Design, Hefei University of Technology
Abstract: This paper presents the hardware implementation of MP3 decoder based on research of MP3 decoding algorithm. Based on the optimization of the decoding algorithm, the register transfer level (RTL) design in Verilog HDL and verification were accomplished, and then field-programmable gate array (FPGA) prototype was implemented based on the StratixII EP2S180 device from ALTERA. The real-time decoding and demo of music playing were performed. The sound effect was desirable. Quantitative analysis showed a signal-to-noise ratio (SNR) of 89 dB, which was beyond the ordinary requirement of MP3 decoding.
Key words: micro-electronics and solid-state electronics; MP3 decoder; hardware architecture; field-programmable gate array prototype
发表期数: 2009年9月第18期
引用格式: 张多利,杜伏慧,杜高明,等. MP3音频解码器的硬件设计与FPGA实现[J]. 中国科技论文在线精品论文,2009,2(18):1879-1883.
 
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