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超动态电压调整SRAM设计

发表时间:2013-11-30  浏览量:1780  下载量:645
全部作者: 赵慧,耿莉
作者单位: 西安交通大学电子与信息工程学院
摘 要: 设计一种8管静态随机存储器(static random access memory,SRAM)单元和相应的读写辅助电路,解决了传统6管SRAM单元低压工作存在的读写稳定性问题,实现了具有超动态电压调整(ultra-dynamic voltage scalable, U-DVS)能力的SRAM设计,其工作电压范围可从亚阈值区变化到标称电压,达到SRAM低功耗和高性能的平衡。通过自适应衬底偏置电路和读缓冲器的设计,增强了SRAM单元低压下的读稳定性(static noise margin, SNM)和鲁棒性。设计可复用的读写辅助电路,同时提高SRAM的低压写能力和读速度。采用标准0.18-μm互补金属-氧化物-半导体(complementary metal-oxide-semiconductor,CMOS)工艺进行流片验证。测试结果表明:SRAM工作电压范围达到0.2~1.8 V,相应的工作频率为184 kHz~208 MHz,0.2~1.8 V的工作电压范围内,SRAM总功耗降低了4个数量级,工作电压0.2 V时的读写功耗仅为30 nW.
关 键 词: 集成电路技术;静态随机存储器;超动态电压调整;亚阈值设计;静态噪声容限;低功耗
Title: An ultra-dynamic voltage scalable SRAM design
Author: ZHAO Hui, GENG Li
Organization: School of Electronic and Information Engineering, Xi�an Jiaotong University
Abstract: This paper presents a novel 8T static random access memory (SRAM) bit-cell and assisted circuit to solve the low-voltage functional problem of 6T SRAM, and achieve the capability of ultra-dynamic voltage scalable (U-DVS) operation. For low voltage operation, the configurable body bias scheme enlarges the static noise margin (SNM) and bit-cell robustness. By multiplexing write and read peripheral assist circuits, SRAM write ability and read speed are both improved. The test-chip is fabricated with a standard 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The measurement results demonstrate that the proposed SRAM can operate from 1.8 V at 208 MHz down to 0.2 V at 184 kHz and the total power dissipation scales down by four orders of magnitude. The access power at 0.2 V supply voltage is 30 nW.
Key words: IC technology; static random access memory; ultra-dynamic voltage scaling; low-voltage design; static noise margin; low power
发表期数: 2013年11月第22期
引用格式: 赵慧,耿莉. 超动态电压调整SRAM设计[J]. 中国科技论文在线精品论文,2013,6(22):2123-2129.
 
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