您的位置:首页  > 论文页面

应用于GSM的快速锁定全数字锁相环设计

发表时间:2013-11-30  浏览量:1447  下载量:790
全部作者: 秦鹏,金晶,张微成,戴煊,周健军
作者单位: 上海交通大学微电子学院
摘 要: 提出一种应用于全球移动通讯系统(global system of mobile communication, GSM)的快速锁定全数字锁相环(all digital phase locked loop,ADPLL)。针对快速锁定的要求,提出将频率控制字预检测技术与自适应带宽技术相结合的方法。该方法大大加快了环路的锁定速度,频率切换时的环路锁定时间为2 μs,满足GSM的要求。设计中采用的数控振荡器达到了1.1 GHz的调谐范围,在工艺角、电压及温度(process voltage and temperature, PVT)偏差存在时都能覆盖住GSM频带。数控振荡器(digital controlled oscillator, DCO)的频率分辨率达到1.632 kHz,远小于GSM的最小信道间隔。包括时间-数字转换器(time-to-digital converter, TDC)、数字鉴相鉴频器(digital phase/frequency detector, DPFD)和数字环路滤波器(digital loop filter, DLF)在内的所有电路都为快速锁定的应用设计。仿真结果显示,ADPLL对输出载波附近的噪声具有足够的抑制。
关 键 词: 电子电路;全数字锁相环;快速锁定;全球移动通讯系统;数字控制振荡器
Title: Design of fast-settling all-digital phase-locked-loop for GSM application
Author: QIN Peng, JIN Jing, ZHANG Weicheng, DAI Xuan, ZHOU Jianjun
Organization: School of Microelectronics, Shanghai Jiaotong University
Abstract: This paper presents a fast settling all-digital phase-locked-loop (ADPLL) for global system of mobile communication (GSM) application. The proposed design adopts frequency word presetting and adaptive bandwidth control to accelerate locking of the loop, which achieves a 2 μs settling time and satisfies GSM requirement. Proposed digital controlled oscillator (DCO) achieves a tuning range of 1.1 GHz, which covers GSM frequency range over process voltage and temperature (PVT). The proposed DCO also achieves a frequency resolution of 1.632 kHz, which is much smaller than GSM channel bandwidth. ADPLL building blocks including time-to-digital converter (TDC), digital phase/frequency detector (DPFD), digital loop filter (DLF) are all redesigned for fast settling application. Simulation results also show that ADPLL provides enough noise suppression at frequencies close to output carrier.
Key words: electronic circuit; MSP430F157; multi-measurement; signal generating; low-power; automatic sleep
发表期数: 2013年11月第22期
引用格式: 秦鹏,金晶,张微成,等. 应用于GSM的快速锁定全数字锁相环设计[J]. 中国科技论文在线精品论文,2013,6(22):2130-2135.
 
0 评论数 0
暂无评论
友情链接