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一种基于单片CPLD的全数字锁相环的设计与实现

发表时间:2017-02-28  浏览量:1426  下载量:327
全部作者: 肖伟翔,沈维聪
作者单位: 武汉理工大学信息工程学院
摘 要: 针对方波信号的倍频和锁相设计一种新型的数字锁相环(digital phase-locked loop,DPLL),其主要功能是实现对中低频方波信号的倍频和锁相,且倍频值可以通过多种接口实时设置,以及输出方波信号的锁相相位可以预设为0°或90°. 该DPLL 是基于复杂可编程逻辑器件(complex programmable logic device,CPLD)的全数字锁相环,由高精度计数器模块、32 位除法器模块、倍频信号发生器、信号分频器、测相位模块、相位补偿模块、计数补偿模块、接口控制模块组成。整个数字系统可将全部算法加载到一片CPLD 芯片之中,使CPLD 芯片被定制成一片DPLL 芯片,以方便该DPLL 应用到各种电路中。
关 键 词: 电子电路;数字锁相环;倍频;复杂可编程逻辑器件
Title: Design and implementation of all-digital phase-locked loop based on single-chip CPLD
Author: XIAO Weixiang, SHEN Weicong
Organization: School of Information Engineering, Wuhan University of Technology
Abstract: In this paper, a new digital phase-locked loop (DPLL) is designed for multiple frequency and phase locking of square wave signal. Its main function is to realize multiple frequency and phase locking of low and medium frequency square wave signal. The frequency doubling value can be set in real time through a variety of interfaces, and the phase-locked phase of the output square wave signal can be preset to 0° or 90°. The DPLL is an all-digital phase-locked loop based on complex programmable logic device (CPLD). It consists of a high-precision counter module, a 32-bit divider module, a multiple frequency signal generator, a signal divider, a phase measurement module, a phase compensation module, a counting compensation module and an interface control module. The entire digital system can load the full algorithm on a CPLD chip, the CPLD chip is customized into a DPLL chip to facilitate the DPLL to be used in a variety of circuits.
Key words: elecronic circuit; digital phase-locked loop; multiple frequency; complex programmable logic device
发表期数: 2017年2月第4期
引用格式: 肖伟翔,沈维聪. 一种基于单片CPLD的全数字锁相环的设计与实现[J]. 中国科技论文在线精品论文,2017,10(4):421-426.
 
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