您的位置:首页  > 论文页面

沟槽MOS 势垒肖特基二极管器件刻蚀工艺优化研究

发表时间:2017-02-28  浏览量:1178  下载量:360
全部作者: 徐晨余
作者单位: 上海交通大学微电子学院
摘 要: 主要阐述了沟槽MOS 势垒肖特基(trench MOS barrier Schottky,TMBS)二极管器件形貌改善的经过及结果,并详细介绍了该类型器件围绕刻蚀工艺变更而对各项工艺的影响。基于器件整体的工艺,研究给出一种在沟槽底部去除二氧化硅的刻蚀工艺的优化解决方案,从而使器件既能够保持原有的特征形貌,还能够提高晶圆的良率和可靠性。
关 键 词: 半导体器件与技术;沟槽MOS 势垒肖特基;功率二极管;刻蚀工艺
Title: Research on the etch process optimization of trench MOS barrier Schottky diode device
Author: XU Chenyu
Organization: School of Microelectronics, Shanghai Jiao Tong University
Abstract: This paper mainly describes the experience and result of improving pattern for trench MOS barrier Schottky (TMBS) diode device, and introduces the influence of all the process from etch process changes of the device. Based on researching of process flow, an etch process optimization of partial removal of silicon oxide under the bottom of the big trench has been put out. The device can not only maintain the characteristic morphology of the original, but also can improve the yield and reliability of wafer.
Key words: semiconductor device and technology; trench MOS barrier Schottky; power diode; etch process
发表期数: 2017年2月第4期
引用格式: 徐晨余. 沟槽MOS 势垒肖特基二极管器件刻蚀工艺优化研究[J]. 中国科技论文在线精品论文,2017,10(4):442-447.
 
1 评论数 0
暂无评论
友情链接