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WAT 引起的晶圆低良率问题研究

发表时间:2018-02-28  浏览量:1607  下载量:395
全部作者: 周波,黄其煜,莫保章
作者单位: 上海交通大学电子信息与电气工程学院;上海华力微电子有限公司
摘 要: 在晶圆制造过程中,部分产品在金属互连层进行晶圆可接受度测试(wafer acceptance test,WAT)时会导致芯片出现特定图形的低良率。本文从WAT引起的缺陷、扎针下压距离(over drive,OD)、不同金属层测试和芯片金属层布线方向等方面分析引起CP失效的原因。验证了CP失效与芯片尺寸和扎针OD呈正相关,但扎针滑动方向与金属层布线方向垂直时不会引起CP失效,并发现其失效位置与金属互连层测试的位置一致。通过选择布线方向合适的金属层进行WAT可解决此问题,提出了一种通过验证的解决方案。
关 键 词: 电子技术;晶圆可接受度测试;金属互连层;低良率;扎针下压距离
Title: Study on the wafer low yield induced by WAT
Author: ZHOU Bo, HUANG Qiyu, MO Baozhang
Organization: School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University; Shanghai Huali Microelectronics Corporation
Abstract: In the wafer manufacture process, some products are tested by wafer acceptance test (WAT) at the metal interconnection layer, resulting in a low yield of chip with particular figure. In this paper, the root cause of the CP failure is analyzed through the defect induced by WAT, probe over drive (OD), different metal layer tests and metal line routing direction. The results show that the CP failure has positive correlation with chip size and probe OD. It will not cause CP failure when the metal line routing direction is vertical with the probe slide direction. The results also show that the location of CP failure is completely matched with the WAT at metal interconnection layer. We propose a suitable line routing direction metal layer for WAT to solve this problem and provide a solution which has been verified.
Key words: electronic technology; wafer acceptance test (WAT); metal interconnection layer; low yield; probe over drive
发表期数: 2018年2月第4期
引用格式: 周波,黄其煜,莫保章. WAT 引起的晶圆低良率问题研究[J]. 中国科技论文在线精品论文,2018,11(4):387-392.
 
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